// Zoom_1 Resource Layout
#define ZOOM_1_CODE_OFFSET	(64L * 1024L)
// Zoom_1 com_2 - RLs B
#define Zoom_1_com_2_rlsatt_ptr		0x0000
#define Zoom_1_com_2_rlsatt_addr		ZOOM_1_CODE_OFFSET + 0x00000000L
#define Zoom_1_com_2_rlsatt_size		8
// Zoom_1 com_2 - RLs Image
#define Zoom_1_com_2_rlscode_addr		ZOOM_1_CODE_OFFSET + 0x000000b4L
#define Zoom_1_com_2_rlscode_size		1732

// Zoom_1 _dummy1_ - RLs B
#define Zoom_1__dummy1__rlsatt_ptr		0x0008
#define Zoom_1__dummy1__rlsatt_addr		ZOOM_1_CODE_OFFSET + 0x00000008L
#define Zoom_1__dummy1__rlsatt_size		4

// Zoom_1 com_1 - RLs C
#define Zoom_1_com_1_rlsatt_ptr		0x000c
#define Zoom_1_com_1_rlsatt_addr		ZOOM_1_CODE_OFFSET + 0x0000000cL
#define Zoom_1_com_1_rlsatt_size		8
// Zoom_1 com_1 - RLs Image
#define Zoom_1_com_1_rlscode_addr		ZOOM_1_CODE_OFFSET + 0x00000778L
#define Zoom_1_com_1_rlscode_size		1804

// Zoom_1 _dummy2_ - RLs C
#define Zoom_1__dummy2__rlsatt_ptr		0x0014
#define Zoom_1__dummy2__rlsatt_addr		ZOOM_1_CODE_OFFSET + 0x00000014L
#define Zoom_1__dummy2__rlsatt_size		4

// Zoom_1 com_0 - RLs D
#define Zoom_1_com_0_rlsatt_ptr		0x0018
#define Zoom_1_com_0_rlsatt_addr		ZOOM_1_CODE_OFFSET + 0x00000018L
#define Zoom_1_com_0_rlsatt_size		8
// Zoom_1 com_0 - RLs Image
#define Zoom_1_com_0_rlscode_addr		ZOOM_1_CODE_OFFSET + 0x00000e84L
#define Zoom_1_com_0_rlscode_size		2416

// Zoom_1 _dummy3_ - RLs D
#define Zoom_1__dummy3__rlsatt_ptr		0x0020
#define Zoom_1__dummy3__rlsatt_addr		ZOOM_1_CODE_OFFSET + 0x00000020L
#define Zoom_1__dummy3__rlsatt_size		4

// Zoom_1 Row_Thread_A Components
#define Zoom_1_Row_Thread_A_thread		0
#define Zoom_1_Row_Thread_A_regaddr		ZOOM_1_CODE_OFFSET + 0x00000000L
#define Zoom_1_Row_Thread_A_regsize		0
// Zoom_1 Row_Thread_B Components
#define Zoom_1_Row_Thread_B_thread		1
#define Zoom_1_Row_Thread_B_regaddr		ZOOM_1_CODE_OFFSET + 0x00000000L
#define Zoom_1_Row_Thread_B_regsize		0
// Zoom_1 Row_Thread_C Components
#define Zoom_1_Row_Thread_C_thread		2
#define Zoom_1_Row_Thread_C_regaddr		ZOOM_1_CODE_OFFSET + 0x00000000L
#define Zoom_1_Row_Thread_C_regsize		0
// Zoom_1 Row_Thread_D Components
#define Zoom_1_Row_Thread_D_thread		3
#define Zoom_1_Row_Thread_D_regaddr		ZOOM_1_CODE_OFFSET + 0x00000000L
#define Zoom_1_Row_Thread_D_regsize		0
// Zoom_1 RLg_Thread_A Components
#define Zoom_1_RLg_Thread_A_thread		0
#define Zoom_1_RLg_Thread_A_regaddr		ZOOM_1_CODE_OFFSET + 0x00000024L
#define Zoom_1_RLg_Thread_A_regsize		16
// Zoom_1 RLg_Thread_B Components
#define Zoom_1_RLg_Thread_B_thread		1
#define Zoom_1_RLg_Thread_B_regaddr		ZOOM_1_CODE_OFFSET + 0x00000034L
#define Zoom_1_RLg_Thread_B_regsize		16
// Zoom_1 RLg_Thread_C Components
#define Zoom_1_RLg_Thread_C_thread		2
#define Zoom_1_RLg_Thread_C_regaddr		ZOOM_1_CODE_OFFSET + 0x00000044L
#define Zoom_1_RLg_Thread_C_regsize		16
// Zoom_1 RLg_Thread_D Components
#define Zoom_1_RLg_Thread_D_thread		3
#define Zoom_1_RLg_Thread_D_regaddr		ZOOM_1_CODE_OFFSET + 0x00000054L
#define Zoom_1_RLg_Thread_D_regsize		16
// Zoom_1 RLs_Thread_A Components
#define Zoom_1_RLs_Thread_A_thread		0
#define Zoom_1_RLs_Thread_A_regaddr		ZOOM_1_CODE_OFFSET + 0x00000064L
#define Zoom_1_RLs_Thread_A_regsize		8
// Zoom_1 RLs_Thread_B Components
#define Zoom_1_RLs_Thread_B_thread		1
#define Zoom_1_RLs_Thread_B_regaddr		ZOOM_1_CODE_OFFSET + 0x0000006cL
#define Zoom_1_RLs_Thread_B_regsize		8
// Zoom_1 RLs_Thread_C Components
#define Zoom_1_RLs_Thread_C_thread		2
#define Zoom_1_RLs_Thread_C_regaddr		ZOOM_1_CODE_OFFSET + 0x00000074L
#define Zoom_1_RLs_Thread_C_regsize		8
// Zoom_1 RLs_Thread_D Components
#define Zoom_1_RLs_Thread_D_thread		3
#define Zoom_1_RLs_Thread_D_regaddr		ZOOM_1_CODE_OFFSET + 0x0000007cL
#define Zoom_1_RLs_Thread_D_regsize		8
// Zoom_1 Win_Thread_A Components
#define Zoom_1_Win_Thread_A_thread		0
#define Zoom_1_Win_Thread_A_regaddr		ZOOM_1_CODE_OFFSET + 0x00000084L
#define Zoom_1_Win_Thread_A_regsize		12
// Zoom_1 Win_Thread_B Components
#define Zoom_1_Win_Thread_B_thread		1
#define Zoom_1_Win_Thread_B_regaddr		ZOOM_1_CODE_OFFSET + 0x00000090L
#define Zoom_1_Win_Thread_B_regsize		12
// Zoom_1 Win_Thread_C Components
#define Zoom_1_Win_Thread_C_thread		2
#define Zoom_1_Win_Thread_C_regaddr		ZOOM_1_CODE_OFFSET + 0x0000009cL
#define Zoom_1_Win_Thread_C_regsize		12
// Zoom_1 Win_Thread_D Components
#define Zoom_1_Win_Thread_D_thread		3
#define Zoom_1_Win_Thread_D_regaddr		ZOOM_1_CODE_OFFSET + 0x000000a8L
#define Zoom_1_Win_Thread_D_regsize		12
// Zoom_1 Mat_Thread_A Components
#define Zoom_1_Mat_Thread_A_thread		0
#define Zoom_1_Mat_Thread_A_regaddr		ZOOM_1_CODE_OFFSET + 0x00000000L
#define Zoom_1_Mat_Thread_A_regsize		0
// Zoom_1 Mat_Thread_B Components
#define Zoom_1_Mat_Thread_B_thread		1
#define Zoom_1_Mat_Thread_B_regaddr		ZOOM_1_CODE_OFFSET + 0x00000000L
#define Zoom_1_Mat_Thread_B_regsize		0
// Zoom_1 Mat_Thread_C Components
#define Zoom_1_Mat_Thread_C_thread		2
#define Zoom_1_Mat_Thread_C_regaddr		ZOOM_1_CODE_OFFSET + 0x00000000L
#define Zoom_1_Mat_Thread_C_regsize		0
// Zoom_1 Mat_Thread_D Components
#define Zoom_1_Mat_Thread_D_thread		3
#define Zoom_1_Mat_Thread_D_regaddr		ZOOM_1_CODE_OFFSET + 0x00000000L
#define Zoom_1_Mat_Thread_D_regsize		0

#define ZOOM_1_RES_SIZE	0x000017f4L

